1. Field of the Invention
The present invention relates to a word line voltage supply circuit, and more particularly to a word line voltage supply circuit configuration directed to reduced power consumption when operating a word line of a DRAM.
2. Description of the Prior Art
A conventional word line voltage supply circuit, such as is shown in FIG. 1, typically comprises row decoder array 20, level converter array 30 for converting the output of each row decoder from voltage level Vcc to voltage level Vpp, word line drivers 40 coupled to row decoders of row decoder array 20, and secondary row decoders 10 for selecting one of word line drivers 40. Secondary row decoders 10 convert signals from voltage level Vcc to voltage level Vpp, which are supplied to word line drivers 40.
Word line drivers 40 receive a voltage level of Vpp from secondary row decoders 10 and drives word lines (WLi) in accordance with the signals of row decoders 20 being of the voltage level Vpp through level converters 30.
The operation of a conventional circuit as described above and illustrated in FIG. 1 will now be discussed. When a memory element is in a standby state, operation of the circuit is conducted so as to maintain row decoder pre-charge signal PC (herein, an underscore in the text is intended to refer to a "barred" or complemented signal in the drawings) at a "low" level, address signals RAi (RA0 to RA3, RAn0 to RAn3) also at "low" levels, level converter outputs RDout1 to RDoutn at a "high" level of voltage Vpp, and the outputs of secondary row decoder 10 (WLD0 to WLD3) at a "low" level.
When the memory element goes to an activated state, that is signal PC becomes a "high" level of voltage Vcc as illustrated in FIG. 2, PMOS transistor Q8 turns off, and PMOS transistor Q9 maintains node C at a "high" level via inverter 22.
When address signals RAi (RA0 to RA3) all become a "high" level of voltage Vcc, transistors Q10, Q11, Q12 and Q13 are turned on, node C becomes a "low" level, and node D becomes a "high" level of voltage Vcc, then transistor Q15 turns off, transistor Q17 turns on, and level converter output RDout1 is changed from a "high" level of voltage Vpp to a "low" level, transistor Q14 turns on, and node E goes to a "high" level of voltage Vpp, and transistor Q16 turns off. Level converter output RDout1 becomes a "low" level, and transistors Q19, Q22, Q25 and Q28 are turned off.
When address signals RF go from a "high" level of voltage Vcc to a "low" level at almost the same timing as address signals RAi as shown in FIG. 2, transistor Q2 turns off, transistor Q3 turns on whereby node B goes from a "high" level of voltage Vcc to a "low" level, transistor Q1 turns on whereby node A goes to a "high" level of voltage Vpp, and thereby transistor Q4 turns off.
With node B at a "low" level, transistor Q5 turns on, transistor Q7 turns off, and secondary row decoder output WLD0 becomes a "high" level of voltage Vpp. When the gate of transistor Q18 becomes a "low" level, whereby transistor Q18 turns on, and secondary row decoder output WLD0 becomes a "high" level of voltage Vpp, word line WL0 also becomes a "high" level of voltage Vpp and thereby becomes selected.
Since one row decoder 20 is coupled to four word lines WL0, WL1, WL2 and WL3 when level converter output RDout1 becomes "low" with NMOS transistors Q19, Q22, Q25 and Q28 turned off, the four word lines selected by one row decoder 20 are connected to ground. Given that the word lines can have a threshold voltage Vtp of an NMOS transistor reached by a noise signal, clamp transistors Q20, Q23, Q26 and Q29 are connected to address signals RF0, RF1, RF2 and RF3. Given that address signals RF1, RF2 and RF3 for word lines that are not selected are "high" level, clamp transistors Q23, Q26 and Q29 are turned on, whereby the word lines WL1, WL2 and WL3 are maintained at ground potential. Level converter output RDoutn maintains a "high" voltage of Vpp at row decoders which are not selected, and thereby, for example, if secondary row decoder output WLD0 goes to a "high" voltage level of Vpp, PMOS transistor Q18 does not turn on.
When the memory element is returned again to a standby state, address signals RAi (RA0 to RA3) become "low" level and address signal RF0 becomes "high" level, and thereby secondary row decoder output WLD0 goes from a "high" level of voltage Vpp to a "low" level. Given that word line WL0 cannot be pulled to a "low" level by PMOS transistor Q18, clamp transistor Q20 is turned on, and a "low" level is applied as signal PC, whereby level converter output RDout1 goes to a "high" level of voltage Vpp, and word line WL0 is pulled to a "low" level.
In word line driver circuit 40, the gate and source signals of transistor Q18, that is RDoutn and WLDi, are signals of voltage level Vpp of an internal voltage supply, and gate signal RFi of clamp transistor Q20 is controlled by a signal of voltage level Vcc.
When assuming that the junction capacitance of a transistor is C.sub.D, and the number of transistors connected to the word line is n, the sum of the junction capacitances becomes nC.sub.D. Assuming that the capacitance of the word line itself is Cw1, and that the capacitance of the secondary row decoder output line is Cm (which is a capacitance of metal wire), capacitance CWLDi of secondary row decoder output WLDi line present when the voltage Vpp is applied is (nC.sub.D +Cw1+Cm).
Since the source node of word line driver 40 is commonly connected to the high voltage level, that is, to secondary row decoder outputs WLDi (i=0, 1, 2, 3) of a voltage level Vpp in prior art devices in order to enable the word line, and given that the sum of the capacitances connected to the word lines CWLDi=(nCD+Cm+Cw1) becomes a load applied to the internal voltage supply (charge pump high voltage supply), the level of the internal voltage supply can become greatly reduced. As a result, the internal voltage level may become unstable, and, while restoring this internal voltage level, a significant amount of power may be consumed.